Xilinx Synthesis Technology User Guide

Procedural Assignments
Verilog Language Support
Procedural assignments are used to assign values to variables
declared as regs and are introduced by always blocks, tasks, and
functions. Procedural assignments are usually used to model
registers and FSMs.
XST includes support for combinatorial functions, combinatorial and
sequential tasks, and combinatorial and sequential always blocks.
Combinatorial Always Blocks
Combinatorial logic can be modeled efficiently using two forms of
time control, the # and @ Verilog time control statements. The # time
control is ignored for synthesis and hence this section describes
modeling combinatorial logic with the @ statement.
A combinatorial always block has a sensitivity list appearing within
parentheses after the word "always @". An always block is activated if
an event (value change or edge) appears on one of the sensitivity list
signals. This sensitivity list can contain any signal that appears in
conditions (If, Case, for example), and any signal appearing on the
right hand side of an assignment. By substituting a * without
parentheses, for a list of signals, the always block is activated for an
event in any of the always block’s signals as described above.
Note In combinatorial processes, if a signal is not explicitly assigned
in all branches of "If" or "Case" statements, XST will generate a latch
to hold the last value. To avoid latch creation, be sure that all assigned
signals in a combinatorial process are always explicitly assigned in all
paths of the process statements.
Different statements can be used in a process:
• Variable and signal assignment
• If... else statement
• Case statement
• For and while loop statement
• Function and task call
The following sections provide examples of each of these statements.
XST User Guide 7-11