Xilinx Synthesis Technology User Guide

XST User Guide
The input and output ports defined in the module declaration called
EXAMPLE are the basic input and output I/O signals for the design.
The inout port in Verilog is analogous to a bi-directional I/O pin on
the device with the data flow for output versus input being
controlled by the enable signal to the tristate buffer. The preceding
example describes E as a tristate buffer with a high-true output
enable signal. If oe = 1, the value of signal A will be output on the pin
represented by E. If oe = 0, then the buffer is in high impedance (Z)
and any input value driven on the pin E (from the external logic) will
be brought into the device and fed to the signal represented by D.
Verilog Assignments
There are two forms of assignment statements in the Verilog
language:
• Continuous Assignments
• Procedural Assignments
Continuous Assignments
Continuous assignments are used to model combinatorial logic in a
concise way. Both explicit and implicit continuous assignments are
supported. Explicit continuous assignments are introduced by the
assign keyword after the net has been separately declared. Implicit
continuous assignments combine declaration and assignment.
Note Delays and strengths given to a continuous assignment are
ignored by XST.
Example of an explicit continuous assignment:
wire par_eq_1;
…...
assign par_eq_1 = select ? b : a;
Example of an implicit continuous assignment:
wire temp_hold = a | b;
Note Continuous assignments are only allowed on wire and tri data
types.
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