Xilinx Synthesis Technology User Guide

Modules
Verilog Language Support
In Verilog a design component is represented by a module. The
connections between components are specified within module
instantiation statements. Such a statement specifies an instance of a
module. Each module instantiation statement must be given a name
(instance name). In addition to the name, a module instantiation
statement contains an association list that specifies which actual nets
or ports are associated with which local ports (formals) of the module
declaration.
All procedural statements occur in blocks that are defined inside
modules. There are two kinds of procedural blocks: the initial block
and the always block. Within each block, Verilog uses a begin and end
to enclose the statements. Since initial blocks are ignored during
synthesis, only always blocks are discussed. Always blocks usually
take the following format:
always
begin
statement
…...
end
where each statement is a procedural assignment line terminated by a
semicolon.
Module Declaration
In the module declaration, the I/O ports of the circuit are declared.
Each port has a name and a mode (in, out, and inout) as shown in the
example below.
module EXAMPLE (A, B, C, D, E);
input A, B, C;
output D;
inout E;
wire D, E;
...
assign E = oe ? A : 1’bz;
assign D = B & E;
...
endmodule
XST User Guide 7-9