Xilinx Synthesis Technology User Guide

Signed/Unsigned Support
Registers
HDL Coding Techniques
When using Verilog or VHDL in XST, some macros, such as adders or
counters, can be implemented for signed and unsigned values.
For Verilog, to enable support for signed and unsigned values, you
have to enable Verilog2001. You can enable it by selecting the Verilog
2001option under the Synthesis Options tab in the Process Properties
dialog box within the Project Navigator, or by setting the -verilog2001
command line option to yes. See the “VERILOG2001” section in the
Constraints Guide for details.
For VHDL, depending on the operation and type of the operands,
you have to include additional packages in your code. For example,
in order to create an unsigned adder, you can use the following
arithmetic packages and types that operate on unsigned values:
PACKAGE TYPE
numeric_std unsigned
std_logic_arith unsigned
std_logic_unsigned std_logic_vector
In order to create a signed adder you can use arithmetic packages and
types that operate on signed values.
PACKAGE TYPE
numeric_std signed
std_logic_arith signed
std_logic_signed std_logic_vector
Please refer to the IEEE VHDL Manual for details on available types.
XST recognizes flip-flops with the following control signals:
• Asynchronous Set/Clear
• Synchronous Set/Clear
• Clock Enable
XST User Guide 2-13