Xilinx Synthesis Technology User Guide

XST User Guide
Data Types
you cannot select more than one element of an array at one time. You
cannot pass multi-dimensional arrays to system tasks or functions, or
regular tasks or functions.
An example of a declaration is shown below:
wire [7:0] array2 [0:255][0:15];
The above describes an array of 256 x 16 wire elements each 8 bits
wide, which can only be assigned via structural Verilog code.
reg [63:0] regarray2 [255:0][7:0];
The above describes an array of 256 x 8 register elements, each 64 bits
wide, which can be assigned via behavioral verilog code.
The Verilog representation of the bit data type contains the following
four values:
• 0: logic zero
• 1: logic one
• x: unknown logic value
• z: high impedance
XST includes support for the following Verilog data types:
• Net: wire, tri, triand/wand, trior/wor
• Registers: reg, integer
• Supply nets: supply0, supply1
• Constants: parameter
• Multi-Dimensional Arrays (Memories)
Net and registers can be either single bit (scalar) or multiple bit
(vectors).
The following example gives some examples of Verilog data types (as
found in the declaration section of a Verilog module).
7-4 Xilinx Development System