Xilinx Synthesis Technology User Guide

Behavioral Verilog Features
Verilog Language Support
This section contains descriptions of the behavioral features of
Verilog.
Variable Declaration
Variables in Verilog may be declared as integers or real. These
declarations are intended only for use in test code. Verilog provides
data types such as reg and wire for actual hardware description.
The difference between reg and wire is whether the variable is given
its value in a procedural block (reg) or in a continuous assignment
(wire) Verilog code. Both reg and wire have a default width being one
bit wide (scalar). To specify an N-bit width (vectors) for a declared
reg or wire, the left and right bit positions are defined in square
brackets separated by a colon. In Verilog 2001, both reg and wire data
types can be signed or unsigned.
Example:
reg [3:0] arb_priority;
wire [31:0] arb_request;
wire signed [8:0] arb_signed;
where arb_request[31] is the MSB and arb_request[0] is the LSB.
Arrays
Verilog allows arrays of reg and wires to be defined as in the
following two examples:
reg [3:0] mem_array [31:0];
The above describes an array of 32 elements each, 4 bits wide which
can be assigned via behavioral verilog code.
wire [7:0] mem_array [63:0];
The above describes an array of 64 elements each 8 bits wide which
can only be assigned via structural Verilog code.
Multi-dimensional Arrays
XST supports multi-dimensional array types of up to two
dimensions. Multi-dimensional arrays can be wire or reg data type.
You can do assignments and arithmetic operations with arrays, but
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