Xilinx Synthesis Technology User Guide

XST User Guide
Introduction
Complex circuits are commonly designed using a top down
methodology. Various specification levels are required at each stage
of the design process. As an example, at the architectural level, a
specification may correspond to a block diagram or an Algorithmic
State Machine (ASM) chart. A block or ASM stage corresponds to a
register transfer block (for example register, adder, counter,
multiplexer, glue logic, finite state machine) where the connections
are N-bit wires. Use of an HDL language like Verilog allows
expressing notations such as ASM charts and circuit diagrams in a
computer language. Verilog provides both behavioral and structural
language structures which allow expressing design objects at high
and low levels of abstraction. Designing hardware with a language
like Verilog allows usage of software concepts such as parallel
processing and object-oriented programming. Verilog has a syntax
similar to C and Pascal, and is supported by XST as IEEE 1364.
The Verilog support in XST provides an efficient way to describe both
the global circuit and each block according to the most efficient
"style". Synthesis is then performed with the best synthesis flow for
each block. Synthesis in this context is the compilation of high-level
behavioral and structural Verilog HDL statements into a flattened
gate-level netlist. which can then be used to custom program a
programmable logic device such as the Virtex FPGA family. Different
synthesis methods will be used for arithmetic blocks, glue logic, and
finite state machines.
This manual assumes that you are familiar with the basic notions of
Verilog. Please refer to the IEEE Verilog HDL Reference Manual for a
complete specification.
7-2 Xilinx Development System