Xilinx Synthesis Technology User Guide

XST User Guide
Table 2-1 VHDL and Verilog Examples and Templates
Macro Blocks Chapter Examples Language Templates
Multiplexers 4-to-1 1-bit MUX using IF
Statement
4-to-1 MUX Using CASE
Statement
4-to-1 MUX Using Tristate
Buffers
No 4-to-1 MUX
Decoders VHDL (One-Hot)
Verilog (One-Hot)
VHDL (One-Cold)
Verilog (One-Cold)
4-to-1 MUX Design with CASE
Statement
4-to-1 MUX Design with Tristate
Construct
1-of-8 Decoder, Synchronous
with Reset
Priority Encoders 3-Bit 1-of-9 Priority Encoder 8-to-3 encoder, Synchronous
with Reset
Logical Shifters Example 1
Example 2
Example 3
None
Dynamic Shifters 16-bit Dynamic Shift Register
with Positive-Edge Clock,
Serial In and Serial Out
None
2-10 Xilinx Development System