Xilinx Synthesis Technology User Guide

VHDL Language Support
Example 6-3 4-bit shift register with Recursive Component
Instantiation
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity single_stage is
generic (sh_st: integer:=4);
port (CLK: in std_logic;
DI : in std_logic;
DO : out std_logic);
end entity single_stage;
architecture recursive of single_stage is
component single_stage
generic (sh_st: integer);
port (CLK: in std_logic;
DI : in std_logic;
DO : out std_logic);
end component;
signal tmp: std_logic;
begin
GEN_FD_LAST: if sh_st=1 generate
inst_fd: FD port map (D=>DI, C=>CLK, Q=>DO);
end generate;
GEN_FD_INTERM: if sh_st /= 1 generate
inst_fd: FD port map (D=>DI, C=>CLK, Q=>tmp);
inst_sstage: single_stage generic map (sh_st
=> sh_st-1) port map
(DI=>tmp, CLK=>CLK, DO=>DO);
end generate;
end recursive;
XST User Guide 6-13