Xilinx Synthesis Technology User Guide

XST User Guide
Example 6-1 Entity and Architecture Declaration
Library IEEE;
use IEEE.std_logic_1164.all;
entity EXAMPLE is
port (A,B,C : in std_logic;
D,E : out std_logic );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
signal T : std_logic;
begin
...
end ARCHI;
Component Instantiation
Structural descriptions assemble several blocks and allow the
introduction of hierarchy in a design. The basic concepts of hardware
structure are the component, the port and the signal. The component
is the building or basic block. A port is a component I/O connector. A
signal corresponds to a wire between components.
In VHDL, a component is represented by a design entity. This is
actually a composite consisting of an entity declaration and an
architecture body. The entity declaration provides the "external" view
of the component; it describes what can be seen from the outside,
including the component ports. The architecture body provides an
"internal" view; it describes the behavior or the structure of the
component.
The connections between components are specified within
component instantiation statements. These statements specify an
instance of a component occurring inside an architecture of another
component. Each component instantiation statement is labeled with
an identifier. Besides naming a component declared in a local
component declaration, a component instantiation statement
contains an association list (the parenthesized list following the
reserved word port map) that specifies which actual signals or ports
are associated with which local ports of the component declaration.
Note XST supports unconstrained vectors in component declarations.
6-10 Xilinx Development System