Xilinx Synthesis Technology User Guide

VHDL Language Support
compiled in the library IEEE. In order to use one of these types, the
following two lines must be added to the VHDL specification:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
The types UNSIGNED and SIGNED (defined as an array of
STD_LOGIC) are declared in the STD_LOGIC_ARITH IEEE package.
This package is compiled in the library IEEE. In order to use these
types, the following two lines must be added to the VHDL
specification:
library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
Multi-dimensional Array Types
XST supports multi-dimensional array types of up to three
dimensions. Arrays can be signals, constants, or VHDL variables. You
can do assignments and arithmetic operations with arrays. You can
also pass multi-dimensional arrays to functions, and use them in
instantiations.
The array must be fully constrained in all dimensions. An example is
shown below:
subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);
type TAB12 is array (11 downto 0) of WORD8;
type TAB03 is array (2 downto 0) of TAB12;
You can also declare and array as a matrix as in the following
example:
subtype TAB13 is array (7 downto 0,4 downto 0)
of STD_LOGIC_VECTOR (8 downto 0);
The following examples demonstrate the various uses of
multi-dimensional array signals and variables in assignments.
Consider the declarations:
subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);
type TAB05 is array (4 downto 0) of WORD8;
type TAB03 is array (2 downto 0) of TAB05;
XST User Guide 6-5