Xilinx Synthesis Technology User Guide

XST User Guide
Verilog example:
module testkeep (in1, in2, out1);
input in1;
input in2;
output out1;
wire aux1;
wire aux2;
// synthesis attribute keep of aux1 is "true"
// synthesis attribute keep of aux2 is "true"
assign aux1 = in1;
assign aux2 = in2;
assign out1 = aux1 & aux2;
endmodule
The KEEP constraint can also be applied through the separate
synthesis constraint file:
XCF Example Syntax:
BEGIN MODEL testkeep
NET aux1 KEEP=true;
END;
Example of Old Syntax:
attribute keep of aux1 : signal is "true";
These are the only two ways of preserving a signal/net in an HDL
design and preventing optimization on the signal or net during
synthesis.
5-54 Xilinx Development System