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Xilinx Synthesis Technology User Guide

Xilinx Synthesis Technology User Guide

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XST <strong>User</strong> <strong>Guide</strong><br />

You may specify the same attribute in the XCF file with the following<br />

lines:<br />

MODEL ENTNAME<br />

NET s PWR_MODE=LOW;<br />

NET s KEEP;<br />

END;<br />

The following statement is written to the NGC file by XST:<br />

NET s PWR_MODE=LOW;<br />

NET s KEEP;<br />

If the attribute applies to an instance (for example, IOB, DRIVE,<br />

IOSTANDARD) and if the instance is not available (not instantiated)<br />

in the HDL source, then the HDL attribute can be applied to the<br />

signal on which XST will infer the instance.<br />

Third Party Constraints<br />

This section describes constraints of third-party synthesis vendors<br />

that are supported by XST. For each of the constraints, Table 5-5 gives<br />

the XST equivalent and indicates when automatic conversion is<br />

available. For information on what these constraints actually do,<br />

please refer to the corresponding vendor documentation. Note that<br />

“NA” stands for “Not Available”.<br />

Table 5-5 Third Party Constraints<br />

Name Vendor XST Equivalent<br />

Available<br />

For<br />

black_box Synplicity box_type VHDL/<br />

Verilog<br />

black_box_pad_pin Synplicity NA NA<br />

black_box_tri_pins Synplicity NA NA<br />

cell_list Synopsys NA NA<br />

clock_list Synopsys NA NA<br />

Directives for inferring FF and<br />

latches<br />

Synopsys NA NA<br />

Enum Synopsys NA NA<br />

5-50 <strong>Xilinx</strong> Development System

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