Xilinx Synthesis Technology User Guide

XST User Guide
Examples
To apply a constraint to specific instances, nets, or pins within an
entity, use one of the two following syntaxes:
BEGIN MODEL EntityName
{NET|INST|PIN}{NetName|InstName|SigName}
PropertyName;
END;
BEGIN MODEL EntityName
{NET|INST|PIN}{NetName|InstName|SigName}
PropertyName=Propertyvalue;
END;
When written in VHDL code, they should be specified as follows:
attribute PropertyName of
{NetName|InstName|PinName} : {signal|label} is
"PropertyValue";
In a Verilog description, they should be written as follows:
// synthesis attribute PropertyName [of]
{NetName|InstName|PinName} [is] "PropertyValue";
Following are three examples.
Example 1
When targeting an FPGA device, the RLOC constraint can be used to
indicate the placement of a design element on the FPGA die relative
to other elements. Assuming a SRL16 instance of name srl1 to be
placed at location R9C0.S0, you may specify the following in your
Verilog code:
// synthesis attribute RLOC of srl1 : "R9C0.S0";
You may specify the same attribute in the XCF file with the following
lines:
BEGIN MODEL ENTNAME
INST sr11 RLOC=R9C0.SO;
END;
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