Xilinx Synthesis Technology User Guide

XST User Guide
This chapter discusses the following Macro Blocks:
• Registers
• Tristates
• Counters
• Accumulators
• Shift Registers
• Dynamic Shift Registers
• Multiplexers
• Decoders
• Priority Encoders
• Logical Shifters
• Arithmetic Operators (Adders, Subtractors, Adders/Subtractors,
Comparators, Multipliers, Dividers, Resource Sharing)
• RAMs
• State Machines
• Black Boxes
For each macro, both VHDL and Verilog examples are given. There is
also a list of constraints you can use to control the macro processing
in XST.
Note For macro implementation details please refer to the “FPGA
Optimization” chapter and the “CPLD Optimization” chapter.
Table 2-1 provides a list of all the examples in this chapter, as well as a
list of VHDL and Verilog synthesis templates available from the
Language Templates in the Project Navigator.
To access the synthesis templates from the Project Navigator:
1. Select Edit → Language Templates...
2. Click the + sign for either VHDL or Verilog.
3. Click the + sign next to Synthesis Templates.
2-6 Xilinx Development System