Xilinx Synthesis Technology User Guide

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XST User Guide Constraint Name incremental- _synthesis iob true, false, auto iostandard string: See Constraints Guide for details yes, no yes, no, true, false true, false, auto signal, instance string: See Constraints Guide for details keep yes, no yes, no true, false keep- _hierarchy yes, no yes, no, true, false entity model no Spartan-II/IIE, Virtex /II/II Pro/E signal, instance loc string string signal (primary IO), instance lut_map yes, no yes, no, true, false net (in model), inst (in model) net (in model), inst (in model) yes Spartan-II/IIE, Virtex /II/II Pro/E no Spartan-II/IIE, Virtex /II/II Pro, XC9500, CoolRunner XPLA3/-II signal net (in model) no Spartan-II/IIE, Virtex /II/II Pro/E, XC9500, CoolRunner XPLA3/-II entity model yes Spartan-II/IIE, Virtex /II/II Pro, XC9500, CoolRunner XPLA3/-II entity. architecture net (in model), inst (in model) max_fanout integer integer entity, signal model, net (in model) move_first- _stage Command Line / Old XST Constraint Syntax Table 5-1 XST-Specific Non-timing Options Values Target XCF Constraint Syntax yes, no yes, no, true, false Command Line / Old XST Constraint Syntax entity, primary clock signal XCF Constraint Syntax no Spartan-II/IIE, Virtex /II/II Pro/E, XC9500, CoolRunner XPLA3/-II model no Spartan-II/IIE, Virtex /II/II Pro/E model, net (in model) Cmd Line Technology yes Spartan-II/IIE, Virtex /II/II Pro/E yes Spartan-II/IIE, Virtex /II/II Pro/E 5-38 Xilinx Development System
Constraint Name move_last- _stage mult_style auto, block, lut yes, no yes, no, true, false mux_extract yes, no, force yes, no, force, true, false mux_style auto, muxf, muxcy entity, primary clock signal model, net (in model) auto, block, lut entity, signal model, net (in model) auto, muxf, muxcy noreduce yes, no yes, no true, false entity, signal model, net (in model) entity, signal model, net (in model) Design Constraints yes Spartan-II/IIE, Virtex /II/II Pro/E yes Virtex-II/II Pro yes Spartan-II/IIE, Virtex /II/II Pro/E, XC9500, CoolRunner XPLA3/-II yes Spartan-II/IIE, Virtex /II/II Pro/E signal net (in model) no XC9500, Cool- Runner XPLA3/ -II opt_level 1, 2 1, 2 entity model yes Spartan-II/IIE, Virtex /II/II Pro/E, XC9500, CoolRunner XPLA3/-II opt_mode speed, area speed, area entity model yes Spartan-II/IIE, Virtex /II/II Pro/E, XC9500, CoolRunner XPLA3/-II priority- _extract Command Line / Old XST Constraint Syntax yes, no, force yes, no, force, true, false ram_extract yes, no yes, no, true, false ram_style auto, block, distributed Table 5-1 XST-Specific Non-timing Options Values Target XCF Constraint Syntax auto, block, distributed Command Line / Old XST Constraint Syntax XCF Constraint Syntax entity, signal model, net (in model) entity, signal model, net (in model) entity, signal model, net (in model) Cmd Line Technology yes Spartan-II/IIE, Virtex /II/II Pro/E yes Spartan-II/IIE, Virtex /II/II Pro/E yes Spartan-II/IIE, Virtex /II/II Pro/E XST User Guide 5-39
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
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Log File Analysis FPGA Optimization
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FPGA Optimization • Tristates Thi
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FPGA Optimization NOTE: THESE TIMIN
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FPGA Optimization The start point a
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FPGA Optimization If the box_type a
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Instantiation of MUXF5 FPGA Optimiz
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Page 247 and 248: Specifying INITs and RLOCs in HDL C
Page 249 and 250: FPGA Optimization for registers onl
Page 251 and 252: PCI Flow FPGA Optimization To succe
Page 253 and 254: CPLD Optimization This chapter cont
Page 255 and 256: Implementation Details for Macro Ge
Page 257 and 258: CPLD Optimization • Final results
Page 259 and 260: CPLD Optimization The CPLD fitter m
Page 261 and 262: Design Constraints Chapter 5 This c
Page 263 and 264: Synthesis Options Design Constraint
Page 265 and 266: Design Constraints Figure 5-4 Synth
Page 267 and 268: • Mux Extraction • Mux Style
Page 269 and 270: Design Constraints For FPGA device
Page 271 and 272: XST Constraint File (XCF) Design Co
Page 273 and 274: Design Constraints Timing Constrain
Page 275 and 276: Design Constraints • Add IO Buffe
Page 277 and 278: Design Constraints the components c
Page 279 and 280: HDL Constraints Design Constraints
Page 281 and 282: FPGA Constraints (non-timing) Desig
Page 283 and 284: Design Constraints • Number of Cl
Page 285 and 286: Design Constraints This constraint
Page 287 and 288: Timing Constraints Design Constrain
Page 289 and 290: Design Constraints See the “CLOCK
Page 291 and 292: Design Constraints The following ti
Page 293 and 294: Design Constraints • TIMEGRP TIME
Page 295 and 296: Design Constraints See the “INPAD
Page 297: Constraint Name clock_buffer bufgdl
Page 301 and 302: Constraint Name xor_collapse yes, n
Page 303 and 304: Constraint Name synthesis/ synopsis
Page 305 and 306: Design Constraints The following ta
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Page 309 and 310: Design Constraints The binary equiv
Page 311 and 312: Table 5-5 Third Party Constraints N
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Page 315 and 316: Constraints Precedence Design Const
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Page 319 and 320: VHDL Language Support 'W' means wea
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Page 323 and 324: Record Types Objects in VHDL MATRIX
Page 325 and 326: Entity Declaration VHDL Language Su
Page 327 and 328: VHDL Language Support Example 6-2 g
Page 329 and 330: VHDL Language Support Example 6-3 4
Page 331 and 332: egin Y 13), port map (X,Y,C1); C2
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Page 337 and 338: Example 6-10 Combinatorial Process
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Page 341 and 342: For...Loop Statement VHDL Language
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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