Xilinx Synthesis Technology User Guide

XST User Guide
Constraints Summary
Constraint
Name
Command
Line
/
Old XST
Constraint
Syntax
attribute or Verilog meta comment may also be used at the VHDL
entity/architecture or Verilog module level.
See the “OFFSET_OUT_AFTER” section in the Constraints Guide
for details.
• Period
The PERIOD constraint optimizes the period of a specific clock
signal. This constraint could be applied to the primary clock
signal. Allowed value is a time value representing the desired
period. There is no default.
This constraint can be set as a VHDL attribute or Verilog meta
comment.
See the “PERIOD” section in the Constraints Guide for details.
Table 5-1 summarizes all available XST-specific non-timing related
options, with allowed values for each, the type of objects they can be
applied to, and usage restrictions. Default values are indicated in
bold.
Table 5-1 XST-Specific Non-timing Options
Values Target
XCF
Constraint
Syntax
Command
Line
/
Old XST
Constraint
Syntax
box_type black_box black_box
XST Constraints
VHDL:
component,
entity
Verilog:
label,
module
bufgce yes, no yes, no,
true, false
primary
clock signal
XCF
Constraint
Syntax
model,
inst (in model)
Cmd
Line
Technology
no Spartan-II/IIE,
Virtex /II/II
Pro/E, XC9500,
CoolRunner
XPLA3
net (in model) no Virtex-II/II Pro
5-36 Xilinx Development System