Xilinx Synthesis Technology User Guide

Design Constraints
See the “INPAD_TO_OUTPAD” section in the Constraints Guide
for details.
• Max Delay
The MAX_DELAY constraint assigns a maximum delay value to
a net. Allowed values are an integer accompanied by a unit.
Allowed units are us, ms, ns, ps, GHz, MHz, and kHz. The default
is ns.
This constraint can be set as a VHDL attribute or Verilog meta
comment.
See the “MAX_DELAY” section in the Constraints Guide for
details.
• Offset In Before
The OFFSET_IN_BEFORE constraint optimizes the maximum
delay from input pad to clock, either for a specific clock or for an
entire design. This constraint can be applied to the top level
entity or the name of the primary clock input. Allowed value is a
time value representing the desired delay. There is no default.
This constraint can be globally set with the Global Optimization
Goal option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator, or with the -
glob_opt offset_in_before command line option. A VHDL
attribute or Verilog meta comment may also be used at the VHDL
entity/architecture or Verilog module level.
See the “OFFSET_IN_BEFORE” section in the Constraints Guide
for details.
• Offset Out After
The OFFSET_OUT_AFTER constraint optimizes the maximum
delay from clock to output pad, either for a specific clock or for
an entire design. This constraint can be applied to the top level
entity or the name of the primary clock input. Allowed value is a
time value representing the desired delay. There is no default.
This constraint can be globally set with the Global Optimization
Goal option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator, or with the -
glob_opt offset_out_after command line option. A VHDL
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