Xilinx Synthesis Technology User Guide

XST User Guide
• Allclocknets
The ALLCLOCKNETS constraint optimizes the period of the
entire design. Allowed values are the name of the top entity
affected and a time value representing the desired period. There
is no default.
This constraint can be globally set with the Global Optimization
Goal option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator, or with the -
glob_opt allclocknets command line option. A VHDL attribute or
Verilog meta comment may also be used at the VHDL entity/
architecture or Verilog module level.
See the “ALLCLOCKNETS” section in the Constraints Guide for
details.
• Duty Cycle
The DUTY_CYCLE constraint assigns a duty cycle to a clock
signal. In the current release, XST does not use this constraint for
optimization or timing estimation, but simply propagates it to the
NGC file. Allowed values are the name of the clock signal
affected and a value expressed as a percentage. There is no
default.
This constraint can be set as a VHDL attribute or Verilog meta
comment.
See the “DUTY_CYCLE” section in the Constraints Guide for
details.
• Inpad To Outpad
The INPAD_TO_OUTPAD constraint optimizes the maximum
delay from input pad to output pad throughout an entire design.
This constraint can be applied to the top level entity. The allowed
value is a time value representing the desired delay. There is no
default.
This constraint can be globally set with the Global Optimization
Goal option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator, or with the
-glob_opt inpad_to_outpad command line option. A VHDL
attribute or Verilog meta comment may also be used at the VHDL
entity/architecture or Verilog module level.
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