Xilinx Synthesis Technology User Guide

Design Constraints
The following timing constraints are supported in the XST
Constraints File (XCF).
• Period
PERIOD is a basic timing constraint and synthesis constraint. A
clock period specification checks timing between all synchronous
elements within the clock domain as defined in the destination
element group. The group may contain paths that pass between
clock domains if the clocks are defined as a function of one or the
other.
See the “PERIOD” section in the Constraints Guide for details.
XCF Syntax:
NET “netname” PERIOD=value [{HIGH | LOW}
value];
• Offset
OFFSET is a basic timing constraint. It specifies the timing
relationship between an external clock and its associated data-in
or data-out pin. OFFSET is used only for pad-related signals, and
cannot be used to extend the arrival time specification method to
the internal signals in a design.
OFFSET allows you to:
♦ Calculate whether a setup time is being violated at a flip-flop
whose data and clock inputs are derived from external nets.
♦ Specify the delay of an external output net derived from the
Q output of an internal flip-flop being clocked from an
external device pin.
See the “OFFSET” section in the Constraints Guide for details.
XCF Syntax:
OFFSET = {IN|OUT} “offset_time” [units]
{BEFORE|AFTER} “clk_name” [TIMEGRP
“group_name”];
XST User Guide 5-31