Xilinx Synthesis Technology User Guide

XST User Guide
♦ XCF timing constraint syntax, which XST supports starting in
release 5.1i. Using the XCF syntax, XST supports constraints
such as TNM_NET, TIMEGRP, PERIOD, TIG, FROM-TO etc.,
including wildcards and hierarchical names.
♦ Old XST timing constraints, which include
ALLCLOCKNETS, PERIOD, OFFSET_IN_BEFORE,
OFFSET_OUT_AFTER, INPAD_TO_OUTPAD and
MAX_DELAY. Please note that these constraints will be
supported in current release, and the next, in the same way
they were supported in release 4.2i without any further
enhancements. Xilinx strongly suggests that you use the
newer XCF syntax constraint style for new devices.
Note Timing constraints are only written to the NGC file when
the Write Timing Constraints property is checked yes in the
Process Properties dialog box in Project Navigator, or the
-write_timing_constraints option is specified when using the
command line. By default, they are not written to the NGC file.
Independent of the way timing constraints are specified, there are
three additional options that effect timing constraint processing:
• Cross Clock Analysis
The CROSS_CLOCK_ANALYSIS command allows inter-clock
domain analysis during timing optimization. By default (NO),
XST does not perform this analysis. See the
“CROSS_CLOCK_ANALYSIS” section in the Constraints Guide
for details.
• Write Timing Constraints
The Write Timing Constraints
(WRITE_TIMING_CONSTRAINTS) option enables or disables
propagation of timing constraints to the NGC file that are
specified in HDL code or the XST constraint file. See the
“WRITE_TIMING_CONSTRAINTS” section in the Constraints
Guide for details.
• Clock Signal
In the case where a clock signal goes through combinatorial logic
before being connected to the clock input of a flip-flop, XST
cannot identify what input pin is the real clock pin. The
CLOCK_SIGNAL constraint allows you to define the clock pin.
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