Xilinx Synthesis Technology User Guide

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XST User Guide • Resynthesize The RESYNTHESIZE constraint forces or prevents resynthesis of an entity or module. See the “RESYNTHESIZE” section in the Constraints Guide for details. • ROM Extraction The ROM Extraction (ROM_EXTRACT) constraint enables or disables ROM macro inference. See the “ROM_EXTRACT” section in the Constraints Guide for details. • Shift Register Extraction The Shift Register Extraction (SHREG_EXTRACT) constraint enables or disables shift register macro inference. See the “SHREG_EXTRACT” section in the Constraints Guide for details. • Slice Packing The Slice Packing (SLICE_PACKING) option enables the XST internal packer. The XST internal packer packs the output of global optimization in the slices. The packer attempts to pack critical LUT-to-LUT connections within a slice or a CLB. This exploits the fast feedback connections among LUTs in a CLB. See the “SLICE_PACKING” section in the Constraints Guide for details. • Uselowskewlines The USELOWSKEWLINES constraint is a basic routing constraint. It specifies the use of low skew routing resources for any net. See the “USELOWSKEWLINES” section in the Constraints Guide for details. • XOR Collapsing The XOR Collapsing (XOR_COLLAPSE) constraint controls whether cascaded XORs should be collapsed into a single XOR. See the “XOR_COLLAPSE” section in the Constraints Guide for details. • Slice Utilization Ratio The SLICE_UTILIZATION_RATIO constraint defines the area size that XST must not exceed during timing optimization. If the constraint cannot be met, XST will make timing optimization regardless of the constraint. 5-24 Xilinx Development System
Design Constraints This constraint can be specified by selecting the Slice Utilization Ratio option under the Synthesis Options tab in the Process Properties dialog box within the Project Navigator, or with the - case command line option. See the “SLICE_UTILIZATION_RATIO” section in the Constraints Guide for details. • Slice Utilization Ratio Delta The SLICE_UTILIZATION_RATIO_MAXMARGIN constraint is closely related to the SLICE_UTILIZATION_RATIO constraint. It defines the tolerance margin for the SLICE_UTILIZATION_RATIO constraint. If the ratio is within the margin set, the constraint is met and timing optimization can continue. For details, see the “Speed Optimization Under Area Constraint.” section of the “FPGA Optimization” chapter, and also see the “SLICE_UTILIZATION_RATIO_MAXMARGIN” section in the Constraints Guide. • Map Entity on a Single LUT The LUT_MAP constraint forces XST to map a single block into a single LUT. If a described function on an RTL level description does not fit in a single LUT, XST will issue an error message. See the “LUT_MAP” section in the Constraints Guide for details. • Read Cores The -read_cores command line switch enables/disables XST to read EDIF/NGC core files for timing estimation and device utilization control. This constraint can be specified by selecting the Read Cores option under the Synthesis Options tab in the Process Properties dialog box within the Project Navigator, or with the -read_cores command line option. See the “READ_CORES” section in the Constraints Guide for details. CPLD Constraints (non-timing) This section lists options that only apply to CPLDs—not FPGAs. • Clock Enable The Clock Enable (PLD_CE) constraint specifies how sequential logic should be implemented when it contains a clock enable, either using the specific device resources available for that or XST User Guide 5-25
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
Page 233 and 234: Log File Analysis FPGA Optimization
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Page 253 and 254: CPLD Optimization This chapter cont
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Page 257 and 258: CPLD Optimization • Final results
Page 259 and 260: CPLD Optimization The CPLD fitter m
Page 261 and 262: Design Constraints Chapter 5 This c
Page 263 and 264: Synthesis Options Design Constraint
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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