Xilinx Synthesis Technology User Guide

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XST User Guide hierarchy of your design. In addition, this constraint is propagated to the NGC file as an implementation constraint. See the “KEEP_HIERARCHY” section in the Constraints Guide for details. • Logical Shifter Extraction The Logical Shifter Extraction (SHIFT_EXTRACT) constraint enables or disables logical shifter macro inference. See the “SHIFT_EXTRACT” section in the Constraints Guide for details. • Max Fanout The Max Fanout (MAX_FANOUT) constraint limits the fanout of nets or signals. See the “MAX_FANOUT” section in the Constraints Guide for details. • Move First Stage The Move First Stage (MOVE_FIRST_STAGE) attribute controls the retiming of registers with paths coming from primary inputs. See the “MOVE_FIRST_STAGE” section in the Constraints Guide for details. • Move Last Stage The Move Last Stage (MOVE_LAST_STAGE) attribute controls the retiming of registers with paths going to primary outputs. See the “MOVE_LAST_STAGE” section in the Constraints Guide for details. • Multiplier Style The Multiplier Style (MULT_STYLE) constraint controls the way the macrogenerator implements the multiplier macros. The implementation style can be manually forced to use block multiplier or LUT resources available in the Virtex-II and Virtex- II Pro devices. See the “MULT_STYLE” section in the Constraints Guide for details. • Mux Style The Mux Style (MUX_STYLE) constraint controls the way the macrogenerator implements the multiplexer macros. See the “MUX_STYLE” section in the Constraints Guide for details. 5-22 Xilinx Development System
Design Constraints • Number of Clock Buffers The Number of Clock Buffers (BUFG) constraint controls the maximum number of BUFGs created by XST. See the “BUFG (XST)” section in the Constraints Guide for details. • Pack I/O Registers into IOBs The Pack I/O Registers into IOBs (IOB) constraint packs flipflops in the I/Os to improve input/output path timing. See the “IOB” section in the Constraints Guide for details. • Priority Encoder Extraction The Priority Encoder Extraction (PRIORITY_EXTRACT) constraint enables or disables priority encoder macro inference. See the “PRIORITY_EXTRACT” section in the Constraints Guide for details. • RAM Extraction The RAM Extraction (RAM_EXTRACT) constraint enables or disables RAM macro inference. See the “RAM_EXTRACT” section in the Constraints Guide for details. • RAM Style The RAM Style (RAM_STYLE) constraint controls whether the macrogenerator implements the inferred RAM macros as block or distributed RAM. See the “RAM_STYLE” section in the Constraints Guide for details. • Register Balancing The Register Balancing (REGISTER_BALANCING) attribute enables flip-flop retiming. See the “REGISTER_BALANCING” section in the Constraints Guide for details. • Register Duplication The Register Duplication (REGISTER_DUPLICATION) constraint enables or disables register replication. See the “REGISTER_DUPLICATION” section in the Constraints Guide for details. XST User Guide 5-23
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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