Xilinx Synthesis Technology User Guide

FPGA Constraints (non-timing)
Design Constraints
This section describes FPGA HDL options. These options apply only
to FPGAs—not CPLDs.
• BUFGCE
The BUFGCE constraint implements BUFGMUX functionality by
inferring a BUFGMUX primitive. This operation reduces the
wiring: clock and clock enable signals are driven to N sequential
components by a single wire. See the “BUFGCE” section in the
Constraints Guide for details.
• Clock Buffer Type
The Clock Buffer Type constraint selects the type of clock buffer
to be inserted on the clock port. See the “CLOCK_BUFFER”
section in the Constraints Guide for details.
• Decoder Extraction
The Decoder Extraction constraint enables or disables decoder
macro inference. See the “DECODER_EXTRACT” section in the
Constraints Guide for details.
• Equivalent Register Removal
The Equivalent Register Removal
(EQUIVALENT_REGISTER_REMOVAL) constraint enables or
disables removal of equivalent registers, described on RTL Level.
XST does not remove equivalent FFs if they are instantiated from
a Xilinx primitive library. See the
“EQUIVALENT_REGISTER_REMOVAL” section in the
Constraints Guide for details.
• Incremental Synthesis
The Incremental Synthesis (INCREMENTAL_SYNTHESIS)
constraint can be applied on a VHDL entity or Verilog module so
that XST generates a single and separate NGC file for it and its
descendents. See the “INCREMENTAL_SYNTHESIS” section in
the Constraints Guide for details.
• Keep Hierarchy
XST may automatically flatten the design to get better results by
optimizing entity/module boundaries. You can use the Keep
Hierarchy (KEEP_HIERARCHY) constraint to preserve the
XST User Guide 5-21