Xilinx Synthesis Technology User Guide

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XST User Guide type. See the “ENUM_ENCODING” section in the Constraints Guide for details. • FSM Encoding Algorithm The FSM Encoding Algorithm (FSM_ENCODING) constraint selects the finite state machine coding technique to be used. The Automatic FSM Extraction option must be enabled in order to select a value for the FSM Encoding Algorithm. See the “FSM_ENCODING” section in the Constraints Guide for details. • FSM Flip-Flop Type The FSM Flip-Flop Type (FSM_FFTYPE) constraint defines what type of flip-flops the state register should implement within an FSM. The only allowed value is d. The t value is not valid for this release. The Automatic FSM Extraction option must be enabled in order to select a value for FSM Flip-Flop Type. See the “FSM_FFTYPE” section in the Constraints Guide for details. • Mux Extraction The Mux Extract (MUX_EXTRACT) constraint enables or disables multiplexer macro inference. For each identified multiplexer description, based on some internal decision rules, XST actually creates a macro or optimizes it with the rest of the logic. See the “MUX_EXTRACT” section in the Constraints Guide for details. • Register Power Up XST will not automatically figure out and enforce register powerup values. You must explicitly specify them if needed with the Register Power Up (REGISTER_POWERUP) constraint. See the “REGISTER_POWERUP” section in the Constraints Guide for details. • Resource Sharing The Resource Sharing (RESOURCE_SHARING) constraint enables or disables resource sharing of arithmetic operators. See the “RESOURCE_SHARING” section in the Constraints Guide for details. 5-20 Xilinx Development System
FPGA Constraints (non-timing) Design Constraints This section describes FPGA HDL options. These options apply only to FPGAs—not CPLDs. • BUFGCE The BUFGCE constraint implements BUFGMUX functionality by inferring a BUFGMUX primitive. This operation reduces the wiring: clock and clock enable signals are driven to N sequential components by a single wire. See the “BUFGCE” section in the Constraints Guide for details. • Clock Buffer Type The Clock Buffer Type constraint selects the type of clock buffer to be inserted on the clock port. See the “CLOCK_BUFFER” section in the Constraints Guide for details. • Decoder Extraction The Decoder Extraction constraint enables or disables decoder macro inference. See the “DECODER_EXTRACT” section in the Constraints Guide for details. • Equivalent Register Removal The Equivalent Register Removal (EQUIVALENT_REGISTER_REMOVAL) constraint enables or disables removal of equivalent registers, described on RTL Level. XST does not remove equivalent FFs if they are instantiated from a Xilinx primitive library. See the “EQUIVALENT_REGISTER_REMOVAL” section in the Constraints Guide for details. • Incremental Synthesis The Incremental Synthesis (INCREMENTAL_SYNTHESIS) constraint can be applied on a VHDL entity or Verilog module so that XST generates a single and separate NGC file for it and its descendents. See the “INCREMENTAL_SYNTHESIS” section in the Constraints Guide for details. • Keep Hierarchy XST may automatically flatten the design to get better results by optimizing entity/module boundaries. You can use the Keep Hierarchy (KEEP_HIERARCHY) constraint to preserve the XST User Guide 5-21
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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Page 233 and 234: Log File Analysis FPGA Optimization
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Page 237 and 238: FPGA Optimization NOTE: THESE TIMIN
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Page 243 and 244: Instantiation of MUXF5 FPGA Optimiz
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Page 247 and 248: Specifying INITs and RLOCs in HDL C
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Page 251 and 252: PCI Flow FPGA Optimization To succe
Page 253 and 254: CPLD Optimization This chapter cont
Page 255 and 256: Implementation Details for Macro Ge
Page 257 and 258: CPLD Optimization • Final results
Page 259 and 260: CPLD Optimization The CPLD fitter m
Page 261 and 262: Design Constraints Chapter 5 This c
Page 263 and 264: Synthesis Options Design Constraint
Page 265 and 266: Design Constraints Figure 5-4 Synth
Page 267 and 268: • Mux Extraction • Mux Style
Page 269 and 270: Design Constraints For FPGA device
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Page 273 and 274: Design Constraints Timing Constrain
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Page 279: HDL Constraints Design Constraints
Page 283 and 284: Design Constraints • Number of Cl
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Page 287 and 288: Timing Constraints Design Constrain
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Page 293 and 294: Design Constraints • TIMEGRP TIME
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Page 297 and 298: Constraint Name clock_buffer bufgdl
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Page 303 and 304: Constraint Name synthesis/ synopsis
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Page 323 and 324: Record Types Objects in VHDL MATRIX
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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