Xilinx Synthesis Technology User Guide

HDL Constraints
Design Constraints
• Verilog 2001
The Verilog 2001(VERILOG2001) command line option
determines if the instance and net names will be written in the
final netlist using all lower or upper case letters or if the case will
be maintained from the source. Note that the case can be
maintained for Verilog synthesis flow only. It can be specified by
selecting the Verilog 2001option under the Synthesis Options tab
in the Process Properties dialog box within the Project Navigator,
or with the -verilog2001 command line option. See the
“VERILOG2001” section in the Constraints Guide for details.
This section describes encoding and extraction constraints. Most of
the constraints can be set globally in the HDL Options tab of the
Process Properties dialog box in Project Navigator. The only
constraint that cannot be set in this dialog box is Enumeration
Encoding. The constraints described in this section apply to FPGAs,
CPLDs, VHDL, and Verilog.
• Automatic FSM Extraction
The Automatic FSM Extraction (FSM_EXTRACT) constraint
enables or disables finite state machine extraction and specific
synthesis optimizations. This option must be enabled in order to
set values for the FSM Encoding Algorithm and FSM Flip-Flop
Type. See the “FSM_EXTRACT” section in the Constraints Guide
for details.
• Complex Clock Enable Extraction
Sequential macro inference in XST generates macros with clock
enable functionality whenever possible. The Complex Clock
Enable Extraction (COMPLEX_CLKEN) constraint instructs or
prevents the inference engine to not only consider basic clock
enable templates, but also look for less obvious descriptions
where the clock enable can be used. See the
“COMPLEX_CLKEN” section in the Constraints Guide for details.
• Enumeration Encoding (VHDL)
The Enumeration Encoding (ENUM_ENCODING) constraint
can be used to apply a specific encoding to a VHDL enumerated
XST User Guide 5-19