Xilinx Synthesis Technology User Guide

XST User Guide
have an extension of .xcf. See the “UC” section in the Constraints
Guide for details.
• Translate Off/Translate On (Verilog/VHDL)
The Translate Off (TRANSLATE_OFF) and Translate On
(TRANSLATE_ON) directives can be used to instruct XST to
ignore portions of your VHDL or Verilog code that are not
relevant for synthesis; for example, simulation code. The
TRANSLATE_OFF directive marks the beginning of the section
to be ignored, and the TRANSLATE_ON directive instructs XST
to resume synthesis from that point. See the “TRANSLATE_OFF
and TRANSLATE_ON” section in the Constraints Guide for
details.
• Use Synthesis Constraints File
The Ignore User Constraints (IUC) command line option allows
you to ignore the constraint file during synthesis. It can be
specified by selecting the Use Synthesis Constraints File option
under the Synthesis Options tab in the Process Properties dialog
box within the Project Navigator, or with the -iuc command line
option. See the “IUC” section in the Constraints Guide for details.
• Verilog Include Directories (Verilog Only)
Use the Verilog Include Directories option (VLGINCDIR) to enter
discrete paths to your Verilog Include Directories. See the
“VLGINCDIR” section in the Constraints Guide for details.
• Verilog Search Paths (Verilog Only)
Use the Verilog Search Paths (VLGPATH) option to enter discrete
paths to your Verilog files. See the “VLGPATH” section in the
Constraints Guide for details.
• VHDL INI File (VHDL Only)
Use the VHDL INI File command (XSTHDPINI) to define the
VHDL library mapping. See the “XSTHDPINI” section in the
Constraints Guide for details.
• VHDL Work Directory (VHDL Only)
Use the VHDL Work Directory command (XSTHDPDIR) to
define VHDL library mapping. See the “XSTHDPDIR” section in
the Constraints Guide for details.
5-18 Xilinx Development System