Xilinx Synthesis Technology User Guide

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XST User Guide • Full Case (Verilog) The FULL_CASE directive is used to indicate that all possible selector values have been expressed in a case, casex, or casez statement. The directive prevents XST from creating additional hardware for those conditions not expressed. See the “Multiplexers” section of the “HDL Coding Techniques” chapter of this manual, and the “FULL_CASE” section in the Constraints Guide for details. • Generate RTL Schematic The Generate RTL Schematic (RTLVIEW) command line option enables XST to generate a netlist file, representing the RTL structure of the design. Note that this netlist generation is not available when Incremental Synthesis Flow is enabled. It can be specified by selecting the Generate RTL Schematic option under the Synthesis Options tab in the Process Properties dialog box within the Project Navigator, or with the -rtlview command line option. See the “RTLVIEW” section in the Constraints Guide for details. • Hierarchy Separator The Hierarchy Separator (HIERARCHY_SEPARATOR) command line option defines the hierarchy separator character that will be used in name generation when the design hierarchy is flattened. It can be specified by selecting the Hierarchy Separator option under the Synthesis Options tab in the Process Properties dialog box within the Project Navigator, or with the -hierarchy_separator command line option. See the “HIERARCHY_SEPARATOR” section in the Constraints Guide for details. • Iostandard Use the IOSTANDARD constraint to assign an I/O standard to an I/O primitive. See the “IOSTANDARD” section in the Constraints Guide for details. • Keep The KEEP constraint is an advanced mapping constraint. When a design is mapped, some nets may be absorbed into logic blocks. When a net is absorbed into a block, it can no longer be seen in the physical design database. This may happen, for example, if 5-16 Xilinx Development System
Design Constraints the components connected to each side of a net are mapped into the same logic block. The net may then be absorbed into the block containing the components. KEEP prevents this from happening. See the “KEEP” section in the Constraints Guide for details. • LOC The LOC constraint defines where a design element can be placed within an FPGA/CPLD. See the “LOC” section in the Constraints Guide for details. • Optimization Effort The Optimization Effort (OPT_LEVEL) constraint defines the synthesis optimization effort level. See the “OPT_LEVEL” section in the Constraints Guide for details. • Optimization Goal The Optimization Goal (OPT_MODE) constraint defines the synthesis optimization strategy. Available strategies can be speed or area. See the “OPT_MODE” section in the Constraints Guide for details. • Parallel Case (Verilog) The PARALLEL_CASE directive is used to force a case statement to be synthesized as a parallel multiplexer and prevents the case statement from being transformed into a prioritized if/elsif cascade. See the “Multiplexers” section of the “HDL Coding Techniques” chapter of this manual. Also see the “PARALLEL_CASE” section in the Constraints Guide for details. • RLOC The RLOC constraint is a basic mapping and placement constraint. This constraint groups logic elements into discrete sets and allows you to define the location of any element within the set relative to other elements in the set, regardless of eventual placement in the overall design. See the “RLOC” section in the Constraints Guide for details. • Synthesis Constraint File The Synthesis Constraint File (UC) command line option creates a synthesis constraints file for XST. It replaces the old one, called ATTRIBFILE, which is obsolete in this release. The XCF must XST User Guide 5-17
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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Page 233 and 234: Log File Analysis FPGA Optimization
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Page 253 and 254: CPLD Optimization This chapter cont
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Page 257 and 258: CPLD Optimization • Final results
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Page 263 and 264: Synthesis Options Design Constraint
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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