Xilinx Synthesis Technology User Guide

XST User Guide
Old XST Constraint Syntax
General Constraints
The constraint file syntax is derived from the VHDL attribute syntax
with a few differences pointed out below. The main difference is that
no attribute declaration is required. An attribute can be directly
specified using the following syntax:
attribute AttributeName of ObjectName : ObjectType is
"AttributeValue" [;]
A statement applies to only one object. A list of object identifiers
cannot be specified in the same statement. Allowed object types are
entity, label, and signal. Attribute values are not typed and should
always be strings. In a hierarchical design, use the following begin
and end statements to access objects in hierarchical units. They are
not required if the considered object is in the top-level unit.
begin UnitName
end UnitName [;]
Example:
begin alu
attribute resource_sharing of result : signal is
"yes" ;
end alu ;
Note that begin and end statements only apply to design units. They
cannot refer to unit instances. As a result, begin and end statements
should never appear inside another begin/end section.
A constraint file can be specified in the Constraint File section of the
Process Properties dialog box in the Project Navigator, or with the
-uc command line option. The option value is a relative or absolute
path to the file.
This section lists various constraints that can be used with XST. These
constraints apply to FPGAs, CPLDs, VHDL, and Verilog. Some of
these options can be set under the Synthesis Options tab of the
Process Properties dialog box within the Project Navigator. See the
“Constraints Summary” section for a complete list of constraints
supported by XST.
5-14 Xilinx Development System