Xilinx Synthesis Technology User Guide

XST User Guide
HDL Options
• Case
• VHDL Work Directory (VHDL Only)
• VHDL INI File (VHDL Only)
• Verilog Search Paths (Verilog Only)
• Verilog Include Directories (Verilog Only)
With the Process Properties dialog box displayed for the Synthesize
process, select the HDL Option tab. For FPGA device families The
following dialog box displays.
Figure 5-5 HDL Options Tab (FPGAs)
Following is a list of all HDL Options that can be set within the HDL
Options tab of the Process Properties dialog box for FPGA devices:
• FSM Encoding Algorithm
• RAM Extraction
• RAM Style
• ROM Extraction
5-6 Xilinx Development System