Xilinx Synthesis Technology User Guide

CPLD Optimization
The CPLD fitter multi-level optimization is still recommended
because of the special optimizations done by the fitter (D to T flipflop
conversion, De Morgan Boolean expression selection).
How to Obtain Better Frequency?
The frequency depends on the number of logic levels (logic depth). In
order to reduce the number of levels, the following options are
recommended:
• Optimization Effort 2: this value implies the calling of the
collapsing algorithm, which tries to reduce the number of levels
without increasing the complexity beyond certain limits.
• Optimization Goal speed: the priority is the reduction of number
of levels.
The following tries, in this order, may give successively better results
for frequency:
Try 1: Select only optimization effort 2 and speed optimization. The
other options have default values:
• Optimization effort 2
• Optimization Goal speed
Try 2: Flatten the user hierarchy. In this case the optimization process
has a global view of the design, and the depth reduction may be
better:
• Optimization effort 1 or 2
• Optimization Goal speed
• Keep Hierarchy no
Try 3: Merge the macros with surrounded logic. The design flattening
is increased:
• Optimization effort 1
• Optimization Goal speed
• Keep Hierarchy no
• Macro Preserve no
XST User Guide 4-7