Xilinx Synthesis Technology User Guide

PCI Flow
FPGA Optimization
To successfully use PCI flow with XST (i.e. to satisfy all placement
constraints and meet timing requirements) set the following options.
• For VHDL designs, ensure that the names in the generated netlist
are all in uppercase. Please note that by default, the case for
VHDL synthesis flow is lower. Specify the case by selecting the
Case option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator.
• For Verilog designs, ensure that the case is set to maintain, which
is a default value. Specify the case as described above.
• Preserve the hierarchy of the design. Specify the Keep Hierarchy
setting can by selecting the Keep Hierarchy option under the
Synthesis Options tab in the Process Properties dialog box within
the Project Navigator.
• Preserve equivalent flip-flops, which XST removes by default.
Specify the Equivalent Register Removal setting can by selecting
the Equivalent Register Removal option under the Xilinx Specific
Options tab in the Process Properties dialog box within the
Project Navigator.
• Prevent logic and flip-flop replication caused by high fanout flipflop
set/reset signals. Do this by:
♦ Setting a high maximum fanout value for the entire design
via the Max Fanout menu in XST Synthesis Options
or
♦ Setting a high maximum fanout value for the initialization
signal connected to the RST port of PCI core by using the
max_fanout attribute (ex. max_fanout=2048).
• Prevent XST from automatically reading PCI cores for timing and
area estimation. In reading PCI cores, XST may perform some
logic optimization in the user’s part of the design that will not
allow the design to meet timing requirements or might even lead
to errors during MAP. Disable Read Cores by unchecking the
Read Cores option under the Synthesis Options tab in the Process
Properties dialog box within the Project Navigator.
Note By default XST reads cores for timing and area estimation.
XST User Guide 3-37