Xilinx Synthesis Technology User Guide

XST User Guide
Moreover, to infer a register in the previous example, and place it in a
specific location of a chip, attach an RLOC constraint to the "tmp"
signal as in the following VHDL example. XST will propagate it to the
final netlist. Please note that this feature is supported for registers
only, but not for inferred RAMs.
library ieee;
use ieee.std_logic_1164.all;
entity test is
port ( CLK : in std_logic;
DI : in std_logic_vector(3 downto 0);
DO : out std_logic_vector(3 downto 0)
);
end test;
architecture beh of test is
signal tmp: std_logic_vector(3 downto
0):="1011";
attribute RLOC: string;
attribute RLOC of tmp: signal is "X3Y0 X2Y0 X1Y0
X0Y0";
begin
process (CLK)
begin
if (clk'event and clk='1') then
tmp