Xilinx Synthesis Technology User Guide

FPGA Optimization
for registers only. It is not supported for RAM descriptions. In the
following VHDL example, a 4-bit register is inferred for signal "tmp".
INIT value equal "1011" is attached to the inferred register and
propagated to the final netlist.
library ieee;
use ieee.std_logic_1164.all;
entity test is
port ( CLK : in std_logic;
DI : in std_logic_vector(3 downto 0);
DO : out std_logic_vector(3 downto 0)
);
end test;
architecture beh of test is
signal tmp: std_logic_vector(3 downto
0):="1011";
begin
process (CLK)
begin
if (clk'event and clk='1') then
tmp