Xilinx Synthesis Technology User Guide

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XST User Guide REZ : out std_logic); attribute LUT_MAP: string; attribute LUT_MAP of my_or: entity is "yes"; end my_or; architecture beh of my_or is begin REZ A, B=>B, REZ=>tmp); inst_or: my_or port map (A=>tmp, B=>C, REZ=>REZ); end beh; If a function cannot be mapped on a single LUT, XST will issue an Error and interrupt the synthesis process. If you would like to define an INIT value for a flip-flop, described at RTL level, you can assign its initial value in the signal declaration stage. This value will not be ignored during synthesis and will be propagated to the final netlist as an INIT constraint attached to the flip-flop. This feature is supported 3-34 Xilinx Development System
FPGA Optimization for registers only. It is not supported for RAM descriptions. In the following VHDL example, a 4-bit register is inferred for signal "tmp". INIT value equal "1011" is attached to the inferred register and propagated to the final netlist. library ieee; use ieee.std_logic_1164.all; entity test is port ( CLK : in std_logic; DI : in std_logic_vector(3 downto 0); DO : out std_logic_vector(3 downto 0) ); end test; architecture beh of test is signal tmp: std_logic_vector(3 downto 0):="1011"; begin process (CLK) begin if (clk'event and clk='1') then tmp
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Page 199 and 200: FSM with 1 Process HDL Coding Techn
Page 201 and 202: Inputs FSM with 2 Processes HDL Cod
Page 203 and 204: Verilog HDL Coding Techniques Follo
Page 205 and 206: process2 : process (state, x1) begi
Page 207 and 208: State Registers HDL Coding Techniqu
Page 209 and 210: Compact HDL Coding Techniques Compa
Page 211 and 212: Black Box Support Log File HDL Codi
Page 213 and 214: Verilog Following is the Verilog co
Page 215 and 216: FPGA Optimization Introduction This
Page 217 and 218: Macro Generation • Number of Cloc
Page 219 and 220: Multiplexers FPGA Optimization For
Page 221 and 222: RAMs FPGA Optimization Two types of
Page 223 and 224: Flip-Flop Retiming FPGA Optimizatio
Page 225 and 226: FPGA Optimization INCREMENTAL_SYNTH
Page 227 and 228: FPGA Optimization Note In the curre
Page 229 and 230: FPGA Optimization generated NGC fil
Page 231 and 232: FPGA Optimization The problem most
Page 233 and 234: Log File Analysis FPGA Optimization
Page 235 and 236: FPGA Optimization • Tristates Thi
Page 237 and 238: FPGA Optimization NOTE: THESE TIMIN
Page 239 and 240: FPGA Optimization The start point a
Page 241 and 242: FPGA Optimization If the box_type a
Page 243 and 244: Instantiation of MUXF5 FPGA Optimiz
Page 245 and 246: Verilog Following is the Verilog co
Page 247: Specifying INITs and RLOCs in HDL C
Page 251 and 252: PCI Flow FPGA Optimization To succe
Page 253 and 254: CPLD Optimization This chapter cont
Page 255 and 256: Implementation Details for Macro Ge
Page 257 and 258: CPLD Optimization • Final results
Page 259 and 260: CPLD Optimization The CPLD fitter m
Page 261 and 262: Design Constraints Chapter 5 This c
Page 263 and 264: Synthesis Options Design Constraint
Page 265 and 266: Design Constraints Figure 5-4 Synth
Page 267 and 268: • Mux Extraction • Mux Style
Page 269 and 270: Design Constraints For FPGA device
Page 271 and 272: XST Constraint File (XCF) Design Co
Page 273 and 274: Design Constraints Timing Constrain
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Page 279 and 280: HDL Constraints Design Constraints
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Page 287 and 288: Timing Constraints Design Constrain
Page 289 and 290: Design Constraints See the “CLOCK
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Page 293 and 294: Design Constraints • TIMEGRP TIME
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Constraint Name move_last- _stage m
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Constraint Name xor_collapse yes, n
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Constraint Name synthesis/ synopsis
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Design Constraints The following ta
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*Also Supported in XCF format. Impl
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Design Constraints The binary equiv
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Table 5-5 Third Party Constraints N
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Table 5-5 Third Party Constraints N
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Constraints Precedence Design Const
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VHDL Language Support Chapter 6 Thi
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VHDL Language Support 'W' means wea
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VHDL Language Support compiled in t
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Record Types Objects in VHDL MATRIX
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Entity Declaration VHDL Language Su
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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