Xilinx Synthesis Technology User Guide

Specifying INITs and RLOCs in HDL Code
FPGA Optimization
Using UNISIM library allows you to directly instantiate LUT
components in your HDL code. To specify a function that a particular
LUT must execute, apply an INIT constraint to the instance of the
LUT. If you want to place an instantiated LUT or register in a
particular slice of the chip, then attach an RLOC constraint to the
same instance.
It is not always convenient to calculate INIT functions and different
methods to can be used to achieve this. Instead, you can describe the
function that you want to map onto a single LUT in your VHDL or
Verilog code in a separate block. Attaching a LUT_MAP constraint
(XST is able to automatically recognize the XC_MAP constraint
supported by Synplicity) to this block will indicate to XST that this
block must be mapped on a single LUT. XST will automatically
calculate the INIT value for the LUT and preserve this LUT during
optimization. In the following VHDL example the "top" block
contains the instantiation of two AND gates, described in "my_and"
and "my_or" blocks. XST generates two LUT2s and does not merge
them. Please refer to the LUT_MAP constraint description in the
Constraint Guide for details.
library ieee;
use ieee.std_logic_1164.all;
entity my_and is
port ( A, B : in std_logic;
REZ : out std_logic);
attribute LUT_MAP: string;
attribute LUT_MAP of my_and: entity is "yes";
end my_and;
architecture beh of my_and is
begin
REZ