Xilinx Synthesis Technology User Guide

Verilog
Following is the Verilog code.
`include "c:\xst\verilog\src\ISE\unisim_comp.v"
module black_b (DI_1, DI_2, SI, DOUT);
input DI_1, DI_2, SI;
output DOUT;
MUXF5 inst (.I0(DI_1), .I1(DI_2), .S(SI), .O(DOUT));
endmodule
Related Constraints
Cores Processing
FPGA Optimization
Related constraints are BOX_TYPE and different PAR constraints that
can be passed from HDL to NGC without processing.
If a design contains cores, represented by an EDIF or an NGC file,
XST is able to automatically read them for timing estimation and area
utilization control. The Read Cores menu from the XST Synthesis
Options in the Process Properties dialog box in Project Navigator
allows you to enable of disable this feature. By default, XST reads
cores. In the following VHDL example, the block "my_add" is an
adder, which is represented as a black box in the design whose netlist
was generated by CoreGen.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity read_cores is
port ( A, B : in std_logic_vector (7 downto 0);
a1, b1: in std_logic;
SUM : out std_logic_vector (7 downto 0);
res : out std_logic);
end read_cores;
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