Xilinx Synthesis Technology User Guide

XST User Guide
Verilog
Following is the Verilog code for instantiation of a MUXF5.
module MUXF5 (O, I0, I1, S);
output 0;
input IO, I1, S;
endmodule
// synthesis attribute BOX_TYPE of MUXF5 is "BLACK_BOX"
module black_b (DI_1, DI_2, SI, DOUT);
input DI_1, DI_2, SI;
output DOUT;
MUXF5 inst (.I0(DI_1), .I1(DI_2), .S(SI), .O(DOUT));
endmodule
Instantiation of MUXF5 with XST Virtex Libraries
Following are VHDL and Verilog examples of an instantiation of a
MUXF5 with XST Virtex Libraries.
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity black_b is
port(DI_1, DI_2, SI : in std_logic;
DOUT : out std_logic);
end black_b;
architecture archi of black_b is
begin
inst: MUXF5 port map (I0=>DI_1, I1=>DI_2, S=>SI, O=>DOUT);
end archi;
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