Xilinx Synthesis Technology User Guide

Instantiation of MUXF5
FPGA Optimization
In this example, the component is directly declared in the HDL
design file.
VHDL
library ieee;
use ieee.std_logic_1164.all;
Following is the VHDL code for instantiation of MUXF5.
entity black_b is
port(DI_1, DI_2, SI : in std_logic;
DOUT : out std_logic);
end black_b;
architecture archi of black_b is
component MUXF5
port (
0 : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
attribute BOX_TYPE: string;
attribute BOX_TYPE of MUXF5: component is "BLACK_BOX";
begin
inst: MUXF5 port map (I0=>DI_1, I1=>DI_2, S=>SI, O=>DOUT);
end archi;
XST User Guide 3-29