Xilinx Synthesis Technology User Guide

FPGA Optimization
If the box_type attribute
• is attached to the MUXF5, XST will try to interpret this module as
a Virtex Primitive. If it is
♦ true, XST will use its parameters, for instance, in critical path
estimation.
♦ false, XST will process it as a regular black box.
• is not attached to the MUXF5. Then XST will process this block as
a Black Box.
In order to simplify the instantiation process, XST comes with VHDL
and Verilog Virtex libraries. These libraries contain the complete set
of Virtex Primitives declarations with a box_type constraint
attached to each component. If you use
• VHDL, then you must declare library "unisim" with its package
"vcomponents" in your source code.
library unisim;
use unisim.vcomponents.all;
The source code of this package can be found in the
"vhdl\src\unisims_vcomp.vhd" file of the XST installation.
• Verilog, then you must include a library file "unisim_comp.v" in
your source code. This file can be found in the "verilog\src\ISE"
directory of the XST installation.
`include "c:\\verilog\src\ISE\unisim_comp.v"
Note If you are using the ISE environment for your Verilog
project, the above is done automatically for you.
Some primitives, like LUT1, allow you to use INIT during
instantiation. In the VHDL case, it is implemented via generic code.
XST User Guide 3-27