Xilinx Synthesis Technology User Guide

XST User Guide
Virtex Primitive Support
XST allows you to instantiate Virtex primitives directly in your
VHDL/Verilog code. Virtex primitives such as MUXCY_L, LUT4_L,
CLKDLL, RAMB4_S1_S16, IBUFG_PCI33_5, and NAND3b2 can be
manually inserted in your HDL design through instantiation. These
primitives are not optimized by XST and will be available in the final
NGC file. Timing information is available for most of the primitives,
allowing XST to perform efficient timing-driven optimization.
Some of these primitives can be generated through attributes:
• clock_buffer can be assigned to the primary input to force the
use of BUFGDLL, IBUFG or BUFGP
• iostandard can be used to assign an I/O standard to an I/O
primitive, for example:
// synthesis attribute IOSTANDARD of in1 is
PCI33_5
will assign PCI33_5 I/O standard to the I/O port.
The primitive support is based on the notion of the black box. Refer to
the “Black Box Support” section of the “HDL Coding Techniques”
chapter for the basics of the black box support.
There is a significant difference between black box and primitive
support. Assume you have a design with a submodule called
MUXF5. In general, the MUXF5 can be your own functional block or
Virtex Primitive. So, in order to avoid confusion about how XST will
interpret this module, you have to use or not use a special constraint,
called box_type. The only possible value for box_type is
black_box. This attribute must be attached to the component
declaration of MUXF5.
3-26 Xilinx Development System