Xilinx Synthesis Technology User Guide

XST User Guide
Gate Net
Cell:in->out fanout Delay Delay Logical Name
---------------------------------------- ------------
FDC:C->Q 15 1.372 2.970 I_state_2
begin scope: 'block1'
LUT3:I1->O 1 0.738 1.265 LUT_54
end scope: 'block1'
LUT3:I0->O 1 0.738 0.000 I_next_state_2
FDC:D 0.440 I_state_2
----------------------------------------
Total 7.523ns
Timing Summary
The Timing Summary section gives a summary of the timing paths
for all 4 domains:
The path from any clock to any clock in the design:
Minimum period: 7.523ns (Maximum Frequency:
132.926MHz)
The maximum path from all primary inputs to the sequential
elements:
Minimum input arrival time before clock: 8.945ns
The maximum path from the sequential elements to all primary
outputs:
Maximum output required time before clock: 14.220ns
The maximum path from inputs to outputs:
Maximum combinational path delay: 10.899ns
If there is no path in the domain concerned "No path found" is then
printed instead of the value.
Timing Detail
The Timing Detail section describes the most critical path in detail for
each region:
3-24 Xilinx Development System