Xilinx Synthesis Technology User Guide

FPGA Optimization
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 9 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 7.523ns (Maximum Frequency: 132.926MHz)
Minimum input arrival time before clock: 8.945ns
Maximum output required time after clock: 14.220ns
Maximum combinational path delay: 10.889ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay: 7.523ns (Levels of Logic = 2)
Source: sdstate_FFD1
Destination: sdstate_FFD2
Source Clock: clk rising
Destination Clock: clk rising
Data Path: sdstate_FFD1 to sdstate_FFD2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 15 1.372 2.970 state_FFD1 (state_FFD1)
LUT3:I1->O 1 0.738 1.265 LUT_54 (N39)
LUT3:I1->O 1 0.738 0.000 I_next_state_2 (N39)
FDC:D 0.440 state_FFD2
----------------------------------------
Total 7.523ns (3.288ns logic, 4.235ns route)
(43.7% logic, 56.3% route)
XST User Guide 3-23