Xilinx Synthesis Technology User Guide

Black Box Support
Log File
HDL Coding Techniques
Your design may contain EDIF or NGC files generated by synthesis
tools, schematic editors, or any other design entry mechanism. These
modules must be instantiated in your code to be connected to the rest
of your design. This can be achieved in XST by using black box
instantiation in the VHDL/Verilog code. The netlist will be
propagated to the final top-level netlist without being processed by
XST. Moreover, XST allows you to attach specific constraints to these
black box instantiations, which will be passed to the NGC file.
Note Remember that once you make a design a black box, each
instance of that design will be black box. While you can attach
constraints to the instance, any constraint attached to the original
design will be ignored.
From the flow point of view, the recognition of black boxes in XST is
done before macro inference process. Therefore the LOG file differs
from the one generated for other macros.
...
Analyzing Entity (Architecture ).
WARNING:Xst:766 - black_box_1.vhd (Line 15). Generating a Black
Box for component .
Entity analyzed. Unit generated
....
Related Constraints
XST has a box_type constraint that can be applied to black boxes.
However, it was introduced essentially for the Virtex Primitive
instantiation in XST. Please read the “Virtex Primitive Support”
section in the “FPGA Optimization” chapter before using this
constraint.
XST User Guide 2-187