Xilinx Synthesis Technology User Guide

State Registers
HDL Coding Techniques
State registers must be initialized with an asynchronous or
synchronous signal. XST does not support FSM without initialization
signals. Please refer to the “Registers” section of this chapter for
templates on how to write Asynchronous and Synchronous
initialization signals.
In VHDL the type of a state register can be a different type: integer,
bit_vector, std_logic_vector, for example. But it is common and
convenient to define an enumerated type containing all possible state
values and to declare your state register with that type.
In Verilog, the type of state register can be an integer or a set of
defined parameters. In the following Verilog examples the state
assignments could have been made like this:
parameter [3:0]
s1 = 4’b0001,
s2 = 4’b0010,
s3 = 4’b0100,
s4 = 4’b1000;
reg [3:0] state;
These parameters can be modified to represent different state
encoding schemes.
Next State Equations
Next state equations can be described directly in the sequential
process or in a distinct combinational process. The simplest template
is based on a Case statement. If using a separate combinational
process, its sensitivity list should contain the state signal and all FSM
inputs.
FSM Outputs
Non-registered outputs are described either in the combinational
process or in concurrent assignments. Registered outputs must be
assigned within the sequential process.
XST User Guide 2-183