05.07.2013 Views

Xilinx Synthesis Technology User Guide

Xilinx Synthesis Technology User Guide

Xilinx Synthesis Technology User Guide

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

HDL Coding Techniques<br />

architecture syn of raminfr is<br />

type ram_type is array (31 downto 0)<br />

of std_logic_vector (3 downto 0);<br />

signal RAM : ram_type;<br />

signal read_add1 : std_logic_vector(4 downto 0);<br />

signal read_add2 : std_logic_vector(4 downto 0);<br />

begin<br />

process (clk1)<br />

begin<br />

if (clk1'event and clk1 = '1') then<br />

if (we = '1') then<br />

RAM(conv_integer(add1))

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!