Xilinx Synthesis Technology User Guide

XST User Guide
The following table shows pin descriptions for a dual-port RAM with
synchronous read (read through) and two clocks.
IO pins Description
clk1 Positive-Edge Write/Primary Read Clock
clk2 Positive-Edge Dual Read Clock
we Synchronous Write Enable (active High)
add1 Write/Primary Read Address
add2 Dual Read Address
di Data Input
do1 Primary Output Port
do2 Dual Output Port
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port (clk1 : in std_logic;
clk2 : in std_logic;
we : in std_logic;
add1 : in std_logic_vector(4 downto 0);
add2 : in std_logic_vector(4 downto 0);
di : in std_logic_vector(3 downto 0);
do1 : out std_logic_vector(3 downto 0);
do2 : out std_logic_vector(3 downto 0));
end raminfr;
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