Xilinx Synthesis Technology User Guide

HDL Coding Techniques
Verilog
Following is the Verilog code for a Division By Constant 2 divider.
module divider(DI, DO);
input [7:0] DI;
output [7:0] DO;
assign DO = DI / 2;
endmodule
Resource Sharing
The goal of resource sharing (also known as folding) is to minimize
the number of operators and the subsequent logic in the synthesized
design. This optimization is based on the principle that two similar
arithmetic resources may be implemented as one single arithmetic
operator if they are never used at the same time. XST performs both
resource sharing and, if required, reduces of the number of
multiplexers that are created in the process.
XST supports resource sharing for adders, subtractors, adders/
subtractors and multipliers.
XST User Guide 2-117