Xilinx Synthesis Technology User Guide

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XST User Guide Multipliers VHDL Following is the VHDL code for an unsigned 8-bit greater or equal comparator. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity compar is port(A,B : in std_logic_vector(7 downto 0); CMP : out std_logic); end compar; architecture archi of compar is begin CMP = B else '0'; end archi; Verilog Following is the Verilog code for an unsigned 8-bit greater or equal comparator. module compar(A, B, CMP); input [7:0] A; input [7:0] B; output CMP; assign CMP = A >= B ? 1'b1 : 1'b0; endmodule When implementing a multiplier, the size of the resulting signal is equal to the sum of 2 operand lengths. If you multiply A (8-bit signal) by B (4-bit signal), then the size of the result must be declared as a 12bit signal. Large Multipliers Using Block Multipliers XST can generate large multipliers using an 18x18 bit block multiplier available in Virtex-II and Virtex-II Pro. For multipliers larger than 2-112 Xilinx Development System
HDL Coding Techniques this, XST can generate larger multipliers using multiple 18x18 bit block multipliers. Registered Multiplier For Virtex-II and Virtex-II Pro, in instances where a multiplier would have a registered output, XST will infer a unique registered multiplier. This registered multiplier will be 18x18 bits. Under the following conditions, a registered multiplier will not be used, and a multiplier + register will be used instead. • Output from the multiplier goes to any component other than the register • The mult_style register is set to lut. • The multiplier is asynchronous. • The multiplier has control signals other than synchronous reset or clock enable. • The multiplier does not fit in a single 18x18 bit block multiplier. The following pins are optional for the registered multiplier. • clock enable port • synchronous and asynchronous reset, reset, and load ports XST User Guide 2-113
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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Log File HDL Coding Techniques The
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 8-bit Shift-L
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Page 89 and 90: Verilog Code HDL Coding Techniques
Page 93 and 94: Dynamic Shift Register module shift
Page 95 and 96: library IEEE; use IEEE.std_logic_11
Page 97 and 98: HDL Coding Techniques The following
Page 99 and 100: neither Full nor Parallel module no
Page 101 and 102: Related Constraints Related constra
Page 103 and 104: HDL Coding Techniques entity mux is
Page 107 and 108: Decoders Log File HDL Coding Techni
Page 109 and 110: VHDL (One-Cold) Following is the VH
Page 111 and 112: VHDL Following is the VHDL code. li
Page 115 and 116: Priority Encoders Log File HDL Codi
Page 117 and 118: Verilog Logical Shifters HDL Coding
Page 119 and 120: Example 1 HDL Coding Techniques The
Page 123 and 124: Verilog Arithmetic Operations Follo
Page 125 and 126: Unsigned 8-bit Adder HDL Coding Tec
Page 127 and 128: HDL Coding Techniques Verilog Follo
Page 131 and 132: Simple Signed 8-bit Adder HDL Codin
Page 133 and 134: Unsigned 8-bit Adder/Subtractor HDL
Page 135: Comparators (=, /=,=) HDL Coding Te
Page 139 and 140: Dividers HDL Coding Techniques VHDL
Page 143 and 144: B C A OPER +/- RES OPER X8984 HDL C
Page 145 and 146: HDL Coding Techniques • RAM descr
Page 147 and 148: HDL Coding Techniques entity raminf
Page 149 and 150: HDL Coding Techniques VHDL The foll
Page 151 and 152: HDL Coding Techniques Verilog The f
Page 153 and 154: HDL Coding Techniques VHDL The foll
Page 155 and 156: Log File HDL Coding Techniques The
Page 157 and 158: VHDL Following is the VHDL code for
Page 159 and 160: HDL Coding Techniques Single-Port R
Page 161 and 162: Verilog HDL Coding Techniques Follo
Page 165 and 166: HDL Coding Techniques Single-Port R
Page 167 and 168: Verilog Following is the Verilog co
Page 169 and 170: VHDL HDL Coding Techniques Followin
Page 171 and 172: Dual-Port RAM with Asynchronous Rea
Page 173 and 174: Verilog Following is the Verilog co
Page 175 and 176: VHDL HDL Coding Techniques Followin
Page 177 and 178: HDL Coding Techniques Dual-Port RAM
Page 181 and 182: HDL Coding Techniques architecture
Page 183 and 184: HDL Coding Techniques Dual-Port RAM
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VHDL HDL Coding Techniques Followin
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Verilog HDL Coding Techniques Follo
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VHDL HDL Coding Techniques Followin
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Verilog Following is the Verilog co
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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Verilog HDL Coding Techniques Follo
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
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Log File Analysis FPGA Optimization
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FPGA Optimization • Tristates Thi
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FPGA Optimization NOTE: THESE TIMIN
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FPGA Optimization The start point a
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FPGA Optimization If the box_type a
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Instantiation of MUXF5 FPGA Optimiz
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Specifying INITs and RLOCs in HDL C
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FPGA Optimization for registers onl
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PCI Flow FPGA Optimization To succe
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CPLD Optimization This chapter cont
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Implementation Details for Macro Ge
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CPLD Optimization • Final results
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CPLD Optimization The CPLD fitter m
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Design Constraints Chapter 5 This c
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Synthesis Options Design Constraint
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Design Constraints Figure 5-4 Synth
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• Mux Extraction • Mux Style
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Design Constraints For FPGA device
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XST Constraint File (XCF) Design Co
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Design Constraints Timing Constrain
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Design Constraints • Add IO Buffe
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Design Constraints the components c
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HDL Constraints Design Constraints
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FPGA Constraints (non-timing) Desig
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Design Constraints • Number of Cl
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Design Constraints This constraint
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Timing Constraints Design Constrain
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Design Constraints See the “CLOCK
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Design Constraints The following ti
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Design Constraints • TIMEGRP TIME
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Design Constraints See the “INPAD
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Constraint Name clock_buffer bufgdl
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Constraint Name move_last- _stage m
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Constraint Name xor_collapse yes, n
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Constraint Name synthesis/ synopsis
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Design Constraints The following ta
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*Also Supported in XCF format. Impl
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Design Constraints The binary equiv
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Table 5-5 Third Party Constraints N
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Table 5-5 Third Party Constraints N
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Constraints Precedence Design Const
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VHDL Language Support Chapter 6 Thi
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VHDL Language Support 'W' means wea
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VHDL Language Support compiled in t
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Record Types Objects in VHDL MATRIX
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Entity Declaration VHDL Language Su
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Verilog Language Support Casez trea
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While Loops Verilog Language Suppor
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Verilog Language Support Example 7-
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Verilog Language Support The main l
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Verilog Language Support • You ca
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Example 7-9 Function Declaration an
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Blocking Versus Non-Blocking Proced
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Include Files Verilog Language Supp
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Verilog Language Support Each insta
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Parameters Verilog Language Support
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Verilog Language Support • Design
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Verilog Meta Comments Verilog Langu
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Table 7-4 Data Types Registers Vect
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Table 7-8 Design Hierarchy Module d
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Verilog Reserved Keywords Verilog L
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Command Line Mode Introduction Chap
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Command Line Mode • Script File
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Command Line Mode • Second column
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Table 8-4 HDL Options (VHDL and Ver
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Command Line Mode Table 8-6 Target
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Command Line Mode • To get a list
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Elaborate Command Time Command Comm
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♦ smallcntr.vhd Command Line Mode
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Command Line Mode You can improve t
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Command Line Mode Sometimes, XST is
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XST Shell Command Line Mode To use
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Case 2 Command Line Mode Each desig
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Log File Analysis Introduction This
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Quiet Mode Timing Report Log File A
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RAM Style : Auto ROM Extraction : y
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Synthesizing Unit . Related source
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# Counters : 2 # 4-bit up counter :
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Log File Analysis Data Path: sixty_
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CPLD Log File Log File Analysis The
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Analyzing Entity (Architecture ).
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Log File Analysis =================
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XST Naming Conventions This appendi
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