Xilinx Synthesis Technology User Guide

XST User Guide
Multipliers
VHDL
Following is the VHDL code for an unsigned 8-bit greater or equal
comparator.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compar is
port(A,B : in std_logic_vector(7 downto 0);
CMP : out std_logic);
end compar;
architecture archi of compar is
begin
CMP = B
else '0';
end archi;
Verilog
Following is the Verilog code for an unsigned 8-bit greater or equal
comparator.
module compar(A, B, CMP);
input [7:0] A;
input [7:0] B;
output CMP;
assign CMP = A >= B ? 1'b1 : 1'b0;
endmodule
When implementing a multiplier, the size of the resulting signal is
equal to the sum of 2 operand lengths. If you multiply A (8-bit signal)
by B (4-bit signal), then the size of the result must be declared as a 12bit
signal.
Large Multipliers Using Block Multipliers
XST can generate large multipliers using an 18x18 bit block multiplier
available in Virtex-II and Virtex-II Pro. For multipliers larger than
2-112 Xilinx Development System